1. Field of the Invention
This invention relates to a voltage detection level correction circuit using a non-volatile memory and to a semiconductor device on which this circuit is mounted.
2. Description of Prior Art
A ferroelectric memory (FeRAM) makes possible reading and writing at a low voltage, as well as high speed operation, in comparison with other non-volatile memories (for example, flash memory or EEPROM). In contrast to this, there is a possibility wherein data rewrite may be carried out even under the condition of a voltage lower than that of a product specification and, therefore, a measure, exceeding the product specification, for preventing malfunction is introduced in the circuit from the point of view of data protection such that a power supply voltage detection circuit is mounted and a command from the outside is not accepted in the case of a voltage lower than, or including, the set voltage.
FIG. 10 shows a block diagram of a semiconductor device on which a ferroelectric memory, which has been conventionally utilized, is mounted. A reference potential generation circuit is denoted as 101, a reference potential output node of the reference potential generation circuit 101 is denoted as NBGRA, a divided voltage potential generation circuit for generating a divided voltage potential is denoted as 102, an output node of the divided voltage potential generation circuit 102 is denoted as NHALA, a differential amplification circuit for generating an output PORA at a CMOS level by amplifying a potential difference between output node NBGRA of reference potential generation circuit 101 and output node NHALA of divided voltage potential generation circuit 101 is denoted as 103, the output node of the differential amplification circuit 103 is denoted as PORA and a power supply voltage detection circuit formed of the reference potential generation circuit 101, the divided voltage potential generation circuit 102 and the differential amplification circuit 103 is denoted as 104. A ferroelectric memory for storing arbitrary information is denoted as 105. A microcomputer logic unit for controlling the ferroelectric memory 105 is denoted as 106.
In the present circuit, in the case that the power supply voltage is lower than the set level, that is to say, in the case that the potential level of node NBGR is higher than the potential level of node NHALA, the logic level of node PORA is set at xe2x80x9cHxe2x80x9d so that the ferroelectric memory 105 and the microcomputer logic unit 106 are converted to the deactivated condition. In addition, in contrast to this, in the case that the power supply voltage is higher than the set level, that is to say, the potential level of node NBGR is lower than the potential level of node NHALA, the logic level of node PORA is set at xe2x80x9cLxe2x80x9d so that the ferroelectric memory 105 and the microcomputer logic unit 106 are converted to the activated condition.
FIG. 11 is a block diagram of a band gap reference circuit showing one example of a reference potential generation circuit.
P channel type CMOS transistors are denoted as QP101, QP102, QP103, QP104 and QP105, N channel type CMOS transistors are denoted as QN101, QN102, QN103 and QN104, resistor elements are denoted as R101, R102 and R103, a differential amplification circuit for amplifying the potential difference between internal nodes N101 and N103 formed of transistors QP103, QP104, QP105, QN102, and QN103 is denoted as 107, diodes are denoted as Di101 and Di102 and the ground voltage is denoted as VSS.
The source of P channel type CMOS transistor QP101 is connected to power supply voltage VDD, and the gate and the drain are connected to node N104. The source of P channel type MOS transistor QP102 is connected to power supply voltage VDD, the gate is connected to node N104, and the drain is connected to node NBGRA. The source of P channel type MOS transistor QP103 is connected to power supply voltage VDD, the gate is connected to node N104, and the drain is connected to N105. The source of P channel type MOS transistor QP104 is connected to node N105, the gate is connected to node N101 and the drain is connected to N106. The source of P channel type MOS transistor QP105 is connected to node N105, the gate is connected to node N103 and the drain is connected to N107.
The gate of N channel type CMOS transistor QN101 is connected to node NBIAS, the source is connected to ground voltage VSS and the drain is connected to node N104. The gate and the drain of N channel type CMOS transistor QN102 are connected to node N106 and the source is connected to ground voltage VSS. The gate of N channel type CMOS transistor QN103 is connected to node N106, the source is connected to ground voltage VSS and the drain is connected to node N107. The gate of N channel type CMOS transistor QN104 is connected to node N107, the source is connected to ground voltage VSS and the drain is connected to node NBGRA.
As for the potential supplied to node NBIAS, a potential slightly higher than the threshold value (Vt) of QN101 is inputted to node NBIAS so that this input allows a constant current to flow through QN101.
The differential amplification circuit 107 is formed of transistors QP103, QP104, QP105, QN102 and QN103 and has nodes N101 and N103 as input terminals, and node N107 as an output terminal. In the case that the level of node N103 is higher than that of node N101, logic potential xe2x80x9cLxe2x80x9d is generated at node N107 and, on the other hand, in the case that the level of node N103 is lower than that of node N101, logic potential xe2x80x9cHxe2x80x9d is generated.
One end of resistor element R101 is connected to node NBGRA and the other end is connected to node N101. One end of resistor element R102 is connected to node N101 and the other end is connected to node N102. One end of resistor element R103 is connected to node NBGRA and the other end is connected to node N103.
The P type diffusion region of diode Di101 is connected to node N103 and the N type diffusion region is connected to ground voltage VSS. The P type diffusion region of diode Di102 is connected to node N102 and the N type diffusion region is connected to ground voltage VSS.
The output voltage VREF at node NBGRA of the band gap reference circuit, shown in FIG. 11, is shown in the following equation (equation 1-1) when the threshold voltage of diode Di101 is denoted as Vd, the resistance values of resistor elements R101, R102 and R103, respectively, are rs11, rs12 and rs13 and the saturation currents of diodes Di101 and Di102, respectively, are Is11 and Is12.
VREF=Vd+(rs11/rs12)*(k/q)*In{(Is12/Is11)*(rs11/rs13)}*Txe2x80x83xe2x80x83(equation 1-1)
wherein the Boltzmann coefficient is denoted as k, the amount of charge of electrons is denoted as q and the absolute temperature is denoted as T.
Vd shown above is dependent on the temperature and has a negative inclination wherein the higher the temperature is, the lower Vd is, while, the lower the temperature is, the higher Vd is.
When the constant voltage portion of the first term, Vd, of the right-side member of (equation 1-1) is denoted as A1, the fluctuation portion thereof due to temperature is denoted as xcex1T, the constant voltage portion of the second term of the right-side member of (equation 1-1) is denoted as B1, and the fluctuation portion thereof due to temperature is denoted as xcex2T, VREF is indicated in the following equation (equation 1-2).
VREF=A1+B1xe2x88x92xcex1T+xcex2Txe2x80x83xe2x80x83(equation 1-2)
The configuration makes it possible to gain a constant reference voltage wherein the dispersion due to the process and to temperature is greatly reduced by setting the values of coefficient xcex1 and xcex2, which are dependent on the temperature, to be equal to each other in (equation 1-2). Though in the present description the circuit configuration of FIG. 11 is used and is explained, other circuit configurations using diodes and register elements can be implemented.
FIG. 12 is a circuit diagram showing an example of divided voltage potential generation circuit 102.
One end of a register element RA101 is connected to power supply voltage VDD and the other end is connected to output node NHALA while one end of register element RA102 is connected to ground voltage VSS and the other end is connected to output node NHALA. The power supply voltage is divided according to a ratio of resistance values of RA101 and RA102 so as to be outputted from node NHALA.
As shown in FIGS. 10 to 12, a band gap reference circuit is, in some cases, used as reference potential generation circuit 101 in order to limit the dispersion of the detection level due to fluctuation in process parameters, or the like, to a small value in power supply voltage detection circuit 104. However, a slight dispersion occurs in the reference potential due to parasitic resistances and parasitic capacitances caused by the layout and due to fluctuation in process parameters inside of a wafer and among wafers. The dispersion in the power supply voltage detection voltage increases in proportion to the power supply voltage detection voltage and the reference potential. In the case that, for example, the ratio of the power supply voltage detection voltage to the reference voltage is 2 and the dispersion in the reference voltage is 50 mV, the dispersion in the power supply voltage detection voltage becomes 100 mV.
In addition, in the case that a differential amplification circuit, shown as 107 in FIG. 11, is used and in the case that, for example, a difference of 30 mV occurs between the threshold values of QP104 and QP105, a nominal difference of 30 mV occurs between nodes N101 and N103 so that a similar dispersion occurs in output node NBGRA, which becomes the reference potential. In the case that a difference occurs between the threshold values of QN102 and QN103, dispersion occurs in output node NBGRA.
In particular, in the case that the values of the communication distance and the power supply voltage become of a tradeoff relationship so that the necessity of tolerance in the low voltage operation increases, such as in a non-contact IC card, reduction of this dispersion becomes important.
Even though fluctuation in the detection voltage level due to temperature variation and due to dispersion in the process can be reduced according to the conventional circuit configuration, it is difficult to correct, in each product, the fluctuation in the detection voltage among respective products caused by process dispersion in the same diffusion lot and in the same wafer, in particular, in the threshold value dispersion among the transistors and it is difficult to adjust the detection voltage level after completion of diffusion and after completion of assembly.
An object of the present invention is to provide a voltage detection level correction circuit and a semiconductor device wherein the power supply detection level can be varied after completion of diffusion as well as after completion of assembly so that it becomes possible to limit the dispersion in the power supply voltage detection level for products to a low level.
A voltage detection level correction circuit of the present invention comprises:
a power supply voltage detection circuit having a reference potential generation circuit for generating a constant reference potential that is independent of the power supply voltage, a divided voltage potential generation circuit for generating a divided potential gained by dividing the above described power supply voltage according to a constant ratio and a differential amplification circuit for comparing the above described reference potential with the above described divided voltage potential and for outputting an output signal in the case that the above described divided potential is lower than the above described reference potential;
a non-volatile memory which stores correction data for correcting the above described reference potential and which is converted to the inactive condition in response to the above described output signal of the above described differential amplification circuit;
a data latch circuit for storing the above described correction data read out from the above described non-volatile memory; and
a control circuit for reading out the above described correction data, which is latched to the above described data latch circuit, from the above described non-volatile memory, and
the voltage detection level correction circuit is characterized in that the above described reference potential generation circuit comprises a circuit which has circuit elements for varying the above described reference potential and which allows the above described correction data to be inputted from the above described data latch circuit for switching of the above described circuit elements.
According to the configuration of this invention, the reference potential can be arbitrarily varied after completion of diffusion and assembly and, therefore, the detection level of the power supply voltage detection circuit can be arbitrarily varied with respect to a product after diffusion and assembly, and it becomes possible to limit the dispersion of the power supply voltage detection level for products to a low level.
In the above described invention, the resistance value of a resistance element existing within the reference potential generation circuit may be altered according to correction data and, thereby, the reference potential is altered.
In addition, in the above described invention, the saturation current value of a diode element existing within the reference potential generation circuit may be altered according to correction data and, thereby, the reference potential is altered.
In the above described invention, the reference potential generation circuit may have a differential amplification circuit formed of transistors and the size of a transistor, of which the gate is connected to an input terminal of the differential amplification circuit, may be altered according to correction data and, thereby, the reference potential is altered.
In the above described invention, the reference potential generation circuit may have a differential amplification circuit that includes a current mirror circuit formed of transistors and the mirror ratio of the current mirror circuit may be altered according to correction data and, thereby, the reference potential is altered.
In the above described invention, at least two, or more, parameters from among the resistance value of the resistance element existing within the reference potential generation circuit, the saturation current value of a diode element existing within the reference potential generation circuit, the size of a transistor of which the gate is connected to an input terminal of a differential amplification circuit formed of transistors existing within the reference potential generation circuit and the mirror ratio of a current mirror circuit in a differential amplification circuit formed of transistors existing within the reference potential generation circuit, may be altered according to correction data and, thereby, the reference potential may be altered.
The above described invention may be characterized in that the above described control circuit operates in response to an output signal of the above described differential amplifier.
According to another aspect of the invention, a voltage detection level correction circuit comprises:
a power supply voltage detection circuit having a reference potential generation circuit for generating a constant reference potential that is independent of the power supply voltage, a divided voltage potential generation circuit for generating a divided potential gained by dividing said power supply voltage according to a constant ratio and a differential amplification circuit for comparing the above described reference potential with the above described divided voltage potential and for outputting an output signal in the case that the above described divided potential is lower than the above described reference potential;
a non-volatile memory which stores correction data for correcting a divided voltage potential in the above described divided voltage potential generation circuit and which is converted to the inactive condition in response to the above described output signal of the above described differential amplification circuit;
a data latch circuit for storing correction data read out from the above described non-volatile memory; and
a control circuit for reading out the above described correction data, which is latched to the above described data latch circuit, from the above described non-volatile memory, and
the voltage detection level correction circuit is characterized in that the above described divided voltage potential generation circuit comprises a circuit which has circuit elements for varying the above described divided voltage potential and which allows the above described correction data to be inputted from the above described data latch circuit for switching of the above described circuit elements.
According to the above described configuration, the divided voltage potential can be arbitrarily varied after diffusion and assembly and, therefore, the power supply detection level can be varied after completion of diffusion and assembly, and it becomes possible to limit the dispersion in the power supply voltage detection level for products to a low level.
The above described invention may be characterized in that the above described control circuit operates in response to an output signal of the above described differential amplifier.
According to yet another aspect of the invention a voltage detection level correction circuit comprises:
a power supply voltage detection circuit having a reference potential generation circuit for generating a constant reference potential that is independent of the power supply voltage, a divided voltage potential generation circuit for generating a divided potential gained by dividing the above described power supply voltage according to a constant ratio and a differential amplification circuit for comparing the above described reference potential with the above described divided voltage potential and for outputting an output signal in the case that the above described divided potential is lower than the above described reference potential;
a non-volatile memory which stores correction data for adjusting the sensitivity of the above described differential amplification circuit and which is converted to the inactive condition in response to the above described output signal of the above described differential amplification circuit;
a data latch circuit for storing correction data read out from the above described non-volatile memory; and
a control circuit for reading out the above described correction data, which is latched to the above described data latch circuit, from the above described non-volatile memory, and
the voltage detection level correction circuit is characterized in that the above described differential amplification circuit comprises a circuit which has circuit elements for adjusting the sensitivity of the above described differential amplification circuit so that the voltage detection level can be corrected and which allows the above described correction data to be inputted from the above described data latch circuit for switching of the above described circuit elements.
According to the above described configuration, the sensitivity of the differential amplification circuit can be arbitrarily adjusted after diffusion and assembly and, therefore, the power supply detection level can be varied after completion of diffusion and assembly, and it becomes possible to limit the dispersion in the power supply voltage detection level for products to a low level.
The above described invention may be characterized in that the above described control circuit operates in response to an output signal of the above described differential amplifier.
According to a further aspect of the invention a voltage detection level correction circuit of the present invention comprises:
a power supply voltage detection circuit having a reference potential generation circuit for generating a constant reference potential that is independent of the power supply voltage, a divided voltage potential generation circuit for generating a divided potential gained by dividing the above described power supply voltage according to a constant ratio and a differential amplification circuit for comparing the above described reference potential with the above described divided voltage potential and for outputting an output signal in the case that the above described divided potential is lower than the above described reference potential;
a non-volatile memory which stores correction data for correcting the above described reference potential, correction data for correcting a divided voltage potential in the above described divided voltage potential generation circuit or correction data for adjusting the sensitivity of the above described differential amplification circuit and which is converted to the inactive condition in response to the above described output signal of the above described differential amplification circuit;
a data latch circuit for storing correction data read out from the above described non-volatile memory; and
a control circuit for reading out the above described correction data, which is latched to said data latch circuit, from the above described non-volatile memory, and
the voltage detection level correction circuit is characterized in that at least two, or more, circuits from among the above described reference potential generation circuit, the above described divided voltage potential generation circuit and the above described differential amplifier comprise circuits which have circuit elements for varying the above described reference potential, the above described divided voltage potential or the sensitivity of the above described differential amplification circuit and which allows the above described correction data to be inputted from the above described data latch circuit for switching of the above described circuit elements.
According to the above described configuration, a semiconductor device can be provided on which a voltage detection level correction circuit that can arbitrarily vary the voltage detection level is mounted so that it becomes possible to limit dispersion in the power supply voltage detection level for products to a low level.
The above described configuration may be characterized in that the above described control circuit operates in response to an output signal of the above described differential amplifier.
A voltage detection level correction circuit having the above described configuration may be mounted on a semiconductor device.